Static Random Access Memories (SRAMs) are known. Logic chips having embedded SRAMs, wherein the memory is formed by cells made of cross-coupled inverters are known. Logic families including SRAMs and BIST macros are also known. Significant advantages are realized by combining logic and memory on the same chip, primarily by avoiding the overhead occurred in communicating between chips. Furthermore, power and space may be reduced and performance significantly improved by providing logic with direct access to an embedded memory. It is a relatively simply matter to include SRAM's in a logic family and, therefore, on chips made from that logic family.
However, DRAMs are another matter. Typically, because of the dichotomy of problems associated with logic versus DRAMs, DRAMs and logic are seldom made on the same manufacturing line, much less combined on the same chip. First, DRAMs require densely packed capacitors with low leakage for storage and, consequently, some form of added processing to create the enhanced capacitor. DRAMs are sensitive to minor defects that do not have a perceptible effect on the logic. Logic often requires extra wiring layers to allow tightly packed logic cells to be interconnected. These are not only unnecessary for DRAMs but, additionally, they could impair the DRAM signal margin and decrease chip yield. Consequently, logic is seldom designed with embedded DRAMs, and DRAMs seldom include significant logic function. BIST logic specifically tests chip function for a limited number of expected results to provide a basic level of confidence to ensure that the chip functions correctly. BIST logic broadly encompasses any function included within a chip (logic or memory).
Another reason DRAM macros are not typically found embedded in logic is that testing a DRAM macro is very complicated. Testing a DRAM chip is in itself a difficult task requiring special test patterns designed to identify specific types of failures, which are eventually combined with specific test voltages and control signal timings. The special test patterns, which include data patterns, address sequencing, timing sequencing change continually as the process goes through changes and matures.
Typical memory BIST techniques employ a state machine wherein the data patterns, address sequencing, control sequence timing are fixed and optimized in the BIST logic. This technique is satisfactory for testing logic and SRAMs. However, it is inadequate for testing DRAMs and especially DRAM macros because of the inflexibility of the BIST logic to cover the data pattern, address sequencing, and control timing sensitivities which can be process or parametric dependent and change with time.
Further, because of DRAM sensitivities to defects, process variations, and other factors that can effect cell signal and functional margins, prior art embedded DRAMs have had fixed images with little or no flexibility built into them. Since each feature (functions, address organization) changes test patterns (data pattern, address sequencing, control timings) that are required and the prediction of how the entire embedded DRAM behaves, prior art embedded DRAMs have been limited to a few basic organizations and then used multiple times with glue logic to create different configurations. Multiple occurrences of the same macro creates the overhead of repeated circuits that can be eliminated with a single embedded DRAM having the desired organization.
Thus, there is a need for a configurable DRAM macro for logic chip designers to select an appropriate configuration without requiring unused, redundant DRAM support circuits. Moreover, there is the need that such a DRAM macro have a flexible BIST that can be externally altered.